Draft, not yet released. In stewardship review. Not indexed until the first approved release.

Exponential Technology Report 2026: Advanced Semiconductors and AI Compute

The first annual edition of the semiconductor and compute report. It fixes the 2026 reference state of advanced semiconductors and AI compute as infrastructure, and the model, voice and positions, against which the 2027 edition will be read.

Read the executive summaryStart with chapter 1Cite this report
Editor
Saeed Valadbaygi
Desk
GCRI Systems Evidence
Publisher of record
GCRI for the Nexus Consortium
Evidence close
30 September 2026
Status
Draft in stewardship review; not yet released
ReportsXT-06

Exponential Technology

Advanced Semiconductors and AI Compute 2026

Baseline Edition 2026NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINEGCRI for the Nexus Consortium
Findings12each with its status and source
Sources44numbered, editor first
Chapters and annexes11plus the executive summary
Indicators16in the data appendix, with CSV and JSON

01 · Status

Status and boundaries.

This edition governs nothing and confers no certification. It records where the global evidence stood at the 2026 baseline. Every value resolves to its source or to its stated method; where neither exists, the edition says so instead of filling the gap.

Publication ID
NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE-v1.0.0
Series alias
NR-XTC-XT-06-2026-BL
Identifier status
Series alias and evidence cut are provisional until the owner confirms them. No UNI is minted.
Family · class
Exponential Technology Report XT-06 · Baseline Edition (inaugural annual)
Lifecycle state
Exponential Technology Report XT-06 · Baseline Edition (inaugural annual)
Publication date
October 2026
Evidence close
30 September 2026 · cut DC-XTECH-SEMICONDUCTORS-GLOBAL-2026-B0
Reproducibility
sourced values cited; analytical values reproducible from stated parameters
Access class
PUBLIC-SAFE DERIVATIVE
Review
five passes scheduled before release (in Annex C)
Designed for
strategic planning · technology-risk screening · readiness discussion · research · public communication
Not for
government assessment · official warning · rating · certification · investment advice · underwriting · procurement · operational authorisation
Registry
record NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE · current-version pointer at release
Corrections
registry correction pathway · history in Annex C
Semiconductor and compute use
disclosed in Annex C
Next edition
NR-XTECH-SEMICONDUCTORS-GLOBAL-2027-v1.0.0 · 2027 annual
Licence
text CC BY 4.0 · data on the terms of each source
Desk identifier
Collection

02 · Key messages

What the edition finds.

Five of the questions the edition answers, each with its status. The executive summary has all of them, with their sources.

  1. USD 791.7 billion in 2025, up 25.6%.

    How big is the chip market?Reported

  2. Performance of leading systems doubled about every nine months since 2019; training compute grows about four times a year.

    How fast is AI compute growing?Reported

  3. US data centres used 176 TWh in 2023; 325 to 580 TWh is projected for 2028.

    What does it need in electricity?Reported

  4. China, Taiwan and Korea took about 79% of 2025 billings.

    Where is equipment bought?Reported

  5. The United States set aside USD 50 billion; the EU recorded over EUR 33 billion in State aid decisions.

    What do governments spend?Reported

All key messages and the headline finding

03 · Contents

Eight chapters and three annexes.

  1. ·

    Executive summary

    The edition on a few pages: the abstract, the key messages, the headline finding and what each steward reads in it.

  2. 1

    Chapter 1. AI compute is physical infrastructure built on a few chips and a few places

    Part I describes systems and their couplings.

  3. 2

    Chapter 2. Key findings

    Twelve findings carry the semiconductor and compute baseline.

  4. 3

    Chapter 3. Systems and sectors at baseline

  5. 4

    Chapter 4. Risks and capability

    Four semiconductor and compute risk objects open the portfolio.

  6. 5

    Chapter 5. Compute build-out meets local power, water and packaging limits

    A conditional statement under stated assumptions, never a prediction.

  7. 6

    Chapter 6. Readings from the other desks

    The semiconductor and compute baseline is read through each steward’s lens, then once as a whole.

  8. 7

    Chapter 7. The 2027 agenda

    Eight bounded questions open the 2027 semiconductor and compute agenda.

  9. 8

    Chapter 8. Systems in depth

    One section per system: its state at evidence close, its exposures and what the operational series will watch.

  10. A

    Annex A. Methodology

    How the edition was made: methods, the model card, the evidence cut and its age, the acceptance record and the glossary.

  11. B

    Annex B. Data appendix

    The indicator set with its sources, the source registers, the licences of every kind of material and the formats of the edition.

  12. C

    Annex C. References and record

    Every source the edition rests on, the publication record, the corrections log and the open record.

List of figures (4)
  1. S.1US data centre electricity use (TWh)
  2. 1.1How fast do compute measures double? Doubling time, months
  3. 1.2Couplings between the five systems
  4. 2.1US data centre electricity use (TWh)
List of tables (45)
  1. 1.1Coupling matrix: from the row system to the column system
  2. 3.1Each domain read in words, not scored
  3. 3.2Sectors: baseline evidence and the exposure to watch
  4. 4.1Capabilities on the ladder of evidence: listed, exists, demonstrated, tested
  5. 6.1The quarterly rhythm every edition follows
  6. 6.2Who contributes what each quarter
  7. 6.32027 semiconductor and compute readiness pack
  8. 6.4Standards and regulatory watch
  9. 6.5Peer-reviewed science and preprints
  10. 6.6Policy and programme sources
  11. 6.7Standards, roadmaps and statutes
  12. 6.8Market, supply and energy overviews
  13. 7.1Objects proposed for the first operational quarter
  14. 7.2Universe 2027: evidence pack for the semiconductor and compute candidate mission
  15. 7.3Handoffs and routing
  16. 7.4Routing rules by publication class
  17. 7.5Feeds watched from 2027
  18. 7.6Signals at baseline
  19. 8.1State at baseline
  20. 8.2State at baseline
  21. 8.3State at baseline
  22. 8.4State at baseline
  23. 8.5State at baseline
  24. A.1Methods
  25. A.2Coupling strength scale (matrix and model card)
  26. A.3Status grammar
  27. A.4From the baseline cut to the federation cut
  28. A.5Evidence age and coverage
  29. A.6Coverage by system at baseline
  30. A.7Designed empty states: what is not bound, what would fill it and why
  31. A.8Quality dimensions at baseline
  32. A.9Publication acceptance record
  33. A.10The status every value carries
  34. A.11Series terms
  35. A.12Abbreviations used in this edition
  36. A.13Technical annex
  37. B.1Global baseline indicator set
  38. B.2Global baseline indicator set
  39. B.3Global source register
  40. B.4Regional reading, semiconductor and compute across ten clusters
  41. B.5How countries appear in the semiconductor and compute edition
  42. B.6National Baseline Editions in the 2026 programme
  43. B.7Licences of each kind of material
  44. B.8This edition in every format
  45. C.1Release path for this version

04 · GCRI reading

How GCRI reads this edition.

The evidence supports reading advanced semiconductors and AI compute as physical infrastructure. Demand growth and sales are well documented, and the footprint of plants and data centres is thinly measured. Evidence is strongest for sales, equipment and US electricity, and weakest for water, packaging and workforce.

AIC-001 · FIN-004 · ENE-007 · SYS-012

Chapter 6, lenses and readings

05 · Publication record

Version, dates and contributors.

The identity of this edition as its title pages record it. A review copy has no DOI; the DOI is issued at deposit.

Publication ID
NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE-v1.0.0
Version
1.0.0, review copy
Edition date
Evidence close
Status
Draft under stewardship review; not yet released
Editor
Saeed Valadbaygi
Publisher of record
The Global Centre for Risk and Innovation (GCRI)
Licence of the text
CC BY 4.0
DOI
Issued at deposit, on release
Previous edition
none: first edition of the series
Next edition
NR-XTECH-SEMICONDUCTORS-GLOBAL-2027-v1.0.0

Contributors

RoleContributionBy
ConceptualisationSeries architecture and the semiconductor and compute modelS. Valadbaygi (ed.)
MethodologyBaseline method, dependency scoring and status grammarReports editorial team, GCRI
Investigation · data curationSource review of semiconductor and compute releases, statistics and the peer-reviewed literature to evidence closeReports editorial team, GCRI
Writing, original draftAll chapters; semiconductor and compute-assisted drafting, disclosed belowEditor · editorial team
Writing, review and editingFive review passes before releaseSteward reviewers (scheduled)
VisualisationPages, figures and tables in the Nexus design standardReports editorial team, GCRI
SupervisionEdition governance, registry record and depositS. Valadbaygi (ed.)

Review before release

PassScopeByState
1Scientific and technicalGCRI · key TScheduled
2Reproducibility of analytical valuesGCRI · key TScheduled
3Public meaning and claimsThe Global Risks Forum (GRF) · key MScheduled
4Finance-readiness boundaryThe Global Risks Alliance (GRA) · key FScheduled
5Regional context, safeguards and dual useRegional consortia · key NScheduled

Semiconductor and compute assistance was used for drafting, consistency checks and page composition. Every number, citation and status label was checked against its source by the editorial team before freeze. No semiconductor and compute system is recorded as an author or a reviewer, and no semiconductor and compute output is printed as fact without a source.

06 · Downloads

Read it in print, take the data.

FormatWhat it isStateGet it
Complete edition, print or PDFA4 or Letter, chosen in the print dialog: cover, contents, every chapter and annex, endnotes and running heads Review copyOpen for print
Indicators, CSV16 indicators with unit, year, status and source On this pageDownload
Indicators, JSONThe same indicators with the edition’s identity and licence On this pageDownload
Findings, CSV12 findings with status, evidence-quality level and references On this pageDownload
Citation, BibTeXFor LaTeX and reference managers On this pageDownload
Citation, RISFor Zotero, EndNote and Mendeley On this pageDownload
PDF, A4 and US LetterPrinted from the edition pack in the Reports print design, with the publication ID, the evidence cut and the pack hash in its metadata; signed with its DOI at release At releaseNot yet issued
Data packageEvery table of the edition as CSV and JSON, with the citation files (CSL-JSON, BibTeX, RIS), built with the site With the editionAnnex B, data

The print and the files are produced from the same edition pack as the web pages, so they always agree. Until release they are review copies.

07 · Cite

Cite this report.

This edition is a draft in stewardship review. Cite it as a draft; the DOI and the UNI are issued at deposit, and the citation then names them.
Catalogue keyNR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE

Standards applied to NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE

Cite as

S. Valadbaygi (ed.), Exponential Technology Report 2026: Advanced Semiconductors and AI Compute. Reports, Baseline Edition 2026. The Global Centre for Risk and Innovation (GCRI) for the Nexus Consortium, Toronto, 2026. NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE. DOI at deposit.

Applied

NS-1 catalogue identity (a UNI is allocated at deposit and resolves to this record), NS-2 citation and attribution, NS-3b dataset metadata, NS-5 figures and maps, NS-12 software and AI disclosure.

Monitoring

Corrections are new versions with a published notice; the earlier version stays resolvable.

An attestation is evidence, not a certificate. Nexus Standards parts are preparatory working drafts (2026).

APA 7
Valadbaygi, S. (Ed.). (2026). Exponential Technology Report 2026: Advanced Semiconductors and AI Compute (Baseline Edition 2026, Report No. NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE) [Draft under review]. The Global Centre for Risk and Innovation (GCRI). https://therisk.global/nexus-reports/editions/xt-06/
Chicago
Valadbaygi, Saeed, ed. Exponential Technology Report 2026: Advanced Semiconductors and AI Compute. Baseline Edition 2026. Nexus Reports NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE. Draft under review. Toronto: The Global Centre for Risk and Innovation (GCRI), 2026. https://therisk.global/nexus-reports/editions/xt-06/.
BibTeX
@techreport{NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE,
  editor      = {Valadbaygi, Saeed},
  title       = {{Exponential Technology Report 2026: Advanced Semiconductors and AI Compute}},
  institution = {The Global Centre for Risk and Innovation (GCRI)},
  address     = {Toronto},
  year        = {2026},
  type        = {Nexus Reports, Baseline Edition 2026},
  number      = {NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE},
  note        = {Draft under stewardship review; not yet released. DOI assigned at deposit},
  url         = {https://therisk.global/nexus-reports/editions/xt-06/}
}
RIS
TY  - RPRT
ED  - Valadbaygi, Saeed
TI  - Exponential Technology Report 2026: Advanced Semiconductors and AI Compute
T3  - Nexus Reports
ET  - Baseline Edition 2026
PY  - 2026
PB  - The Global Centre for Risk and Innovation (GCRI)
CY  - Toronto
SN  - NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE
UR  - https://therisk.global/nexus-reports/editions/xt-06/
N1  - Draft under stewardship review; not yet released. DOI assigned at deposit.
LA  - en
ER  -
NR-CIT-1 (house style)
S. Valadbaygi (ed.), Exponential Technology Report 2026: Advanced Semiconductors and AI Compute. Nexus Reports, Baseline Edition 2026. The Global Centre for Risk and Innovation (GCRI) for the Nexus Consortium, Toronto, 2026. NR-XTECH-SEMICONDUCTORS-GLOBAL-2026-BASELINE. DOI at deposit.
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